The present invention relates to a class D amplifier (digital amplifier) which converts an analog signal such as a music signal to a pulse signal, and power-amplifies the signal, and more particularly to a circuit technique for driving and controlling output power MOS-transistors.
Conventionally, a class D amplifier is known which receives an analog signal such as a music signal as an input signal, converts the signal to a pulse signal, and then power-amplifies the signal. An output terminal of the amplifier is connected to an input terminal of a loudspeaker via a low-pass filter. In such a class D amplifier, a pulse signal is power-amplified while reflecting the amplitude of the input signal to the pulse width, and the pulse signal is output. The pulse signal is then passed through the external low-pass filter, whereby the analog music signal is extracted, so that the loudspeaker is driven by the signal. A class D amplifier can be formed on a silicon chip, and hence is widely used in a portable terminal device or a personal computer which is requested to consume a small power.
A conventional class D amplifier will be described with reference to FIG. 1. Referring to the figure, a signal source SIG is a source of an analog music signal VIN in which the midpoint of the amplitude is set to the ground potential (0 V), and connected to an input terminal TI via an input capacitor CIN. The class D amplifier is a so-called PWM amplifier (PWM: Pulse Width Modulation), and configured by an input stage 100, a modulating circuit 200, a drive controlling circuit 300, and n-type power-MOS transistors 401 and 402.
The input stage 100 converts the waveform of the music signal VIN to a voltage (amplitude) conforming to the input characteristics of the modulating circuit 200. The modulating circuit 200 is disposed subsequently to the input stage, and converts the music signal supplied from the input stage 100 to a pulse signal (PWM modulation). On the basis of the modulated pulse signal, the drive controlling circuit 300 complementarily drives the output power-MOS transistors 401 and 402. The power-MOS transistor 401 is used for outputting a high level, and the power-MOS transistor 402 for outputting a low level. An input terminal of a loudspeaker SPK is connected to an output terminal TO via a low-pass filter consisting of an inductor L and a capacitor C.
In the class D amplifier, the music signal VIN supplied from the signal source SIG is passed through the input stage 100 and the modulating circuit 200 to be converted to a pulse signal. On the basis of the modulated pulse signal, the drive controlling circuit 300 complementarily controls the conduction states of the power-MOS transistors 401 and 402, and outputs the power-amplified pulse signal to the output terminal TO. In the power-amplified pulse signal, the carrier frequency component is removed away by the low-pass filter consisting of the inductor L and the capacitor C, and then the signal is supplied to the loudspeaker SPK.
The modulating circuit 200 is configured so as to be operated by a single power supply VDD (for example, 10 V). Consequently, the low level of the pulse signal which is the output signal of the circuit is equal to the ground potential (0 V), and the high level is equal to the voltage (10 V) supplied from the power supply VDD. Therefore, when the pulse signal having such signal levels is used as it is, the power-MOS transistor 401 in which the drain is connected to a positive power supply VPP+ (for example, +50 V) cannot be sufficiently controlled to the on state because of the characteristics of a MOS transistor, and the power-MOS transistor 402 in which the source is connected to a negative power supply VPP− (for example, −50 V) cannot be sufficiently controlled to the off state. Therefore, the drive controlling circuit 300 is configured so as to be able to control the power-MOS transistors 401 and 402 on the basis of the pulse signal which is modulated in the modulating circuit 200, and comprises so-called high- and low-side drivers.
In an actual usage situation of a class D amplifier, a speaker terminal is formed as an external terminal, and there is the possibility that the output terminal is short-circuited to ground. In the case where the output terminal is short-circuited to ground, when a power-MOS transistor in the output stage is in the on state, an overcurrent which exceeds the allowable current flows through the power-MOS transistor, thereby causing a fear that the output stage is broken. Therefore, a countermeasure is taken to protect the power-MOS transistor in the output stage from an overcurrent.
FIG. 7 shows an example of a configuration for protecting a power-MOS transistor in the output stage from an overcurrent. Referring to the figure, signals H3 and H4 are signals respectively having the same and negative-phases as that of the pulse signal which is output from the above-mentioned modulating circuit 200, and the signals are used as input signals of the high-side driver. Signals L3 and L4 are signals respectively having the same and negative-phases as that of the pulse signal which is output from the modulating circuit 200, and the signals are used as input signals of the low-side driver. A driving circuit 303HJ functions as the high-side driver, and, on the basis of the signals H3 and H4, drives the power-MOS transistor 401. A driving circuit 303LJ functions as the low-side driver, and, on the basis of the signals L3 and L4, drives the power-MOS transistor 402.
A resistor RS1 is used for detecting a current flowing through the power-MOS transistor 401, and connected between the power-MOS transistor 401 and the output terminal TO. A resistor RS2 is used for detecting a current flowing through the power-MOS transistor 402, and connected between the power-MOS transistor 402 and the negative power supply VPP−. In the driving circuit 303HJ, a comparator CM1, an AND gate circuit AN1, and a buffer B14 are disposed so as to constitute a transfer path for the signals H3 and H4, and a comparator CM11 and a latch LA1 are disposed so as to constitute a circuit system for detecting an overcurrent. The non-inverting input of the comparator CM11 is connected to one end of the resistor RS1, and the inverting input terminal of the comparator is connected to the other end of the resistor. RS1 via a reference power supply REFH. The reference power supply REFH is set so that, when an overcurrent which exceeds the allowable current flows through the resistor RS1, the output of the comparator CM11 is inverted. An output of the comparator CM11 is connected to a negative logic input of the AND gate; circuit AN1 via the latch LA1. The other driving circuit 303LJ is configured by a comparator CM2, an AND gate circuit AN2, a buffer B24, a reference power supply REFL, a comparator CM21, and a latch LA2. These components correspond to the comparator CM1, the AND gate circuit AN1, and the buffer B14, the reference power supply REFH, the comparator CM11, and the latch LA1 which constitute the above-mentioned driving circuit 303HJ, respectively.
An operation of detecting an overcurrent will be described. When an overcurrent occurs in the power-MOS transistor 401, for example, a voltage is generated across the ends of the resistor RS1. When the voltage exceeds the voltage of the reference power supply REFH, the output of the comparator CM11 has a high level. The high level is latched by the latch LA1, and then supplied to the negative logic input of the AND gate circuit AN1. Therefore, the output signal of the AND gate circuit AN1 is set to a low level, and then supplied to the gate of the power-MOS transistor. 401 via the buffer B14. As a result, the power-MOS transistor 401 is controlled to the off state, whereby the overcurrent is interrupted. Consequently, the power-MOS transistor 401 is protected from the overcurrent. When an overcurrent flows through the power-MOS transistor 402, similarly, a voltage is generated across the ends of the resistor RS2. When the voltage exceeds the voltage of the reference power supply REFL, the output of the comparator CM21 has a high level, and the high level is supplied to the negative logic input of the AND gate circuit AN2. Therefore, the output signal of the AND gate circuit AN2 is set to a low level, and the power-MOS transistor 402 is controlled to the off state.
In the conventional art of protecting an output stage from an overcurrent, the driving circuits 303HJ and 303LJ separately detect an overcurrent to control the power-MOS transistors 401 and 402. Therefore, an operation status where only one of the power-MOS transistors is controlled to the off state and the other power-MOS transistor is set to an operable state may occur. Such a status is not preferable in the operation of a system in which the class D amplifier is mounted.